1. Field of the Invention
This invention relates generally to semiconductor devices. More particularly, the invention pertains to apparatus for suppressing undesirable high frequency induction noise in high speed integrated circuits (ICs).
2. State of the Art
Modern semiconductor devices including integrated circuit (IC) devices, such as DRAM and SRAM devices have electrically conductive internal leads and output drivers which are switched ON and OFF. The switching operations between no current and peak current is very rapid and may cause rapid changes in the power supply voltage and spikes within the lead circuits and the die circuits. Such induced voltage and current variations cause malfunctions of the integrated circuit and may severely limit the clock speed at which the device may be satisfactorily operated. The problem is particularly relevant in devices having a large number of leads, where many leads may be simultaneously switched ON to cause a large, sudden current drain.
The goal of decoupling capacitors is to provide a system whereby the actual ranges of voltage and current in each part of the circuit during the ON and OFF stages are relatively narrow, i.e. positive and negative spikes are avoided, even at high frequency operation.
A typical semiconductor device comprises a semiconductor die, leads for connecting the die circuit to a host apparatus, and packaging for enclosing and sealing the device. The leads are generally formed as part of a lead frame constructed from a metal foil or as a metal film on a polymeric base such as in tape automated bonding (TAB).
In a typical conventional device configuration, a conductive lead frame includes a xe2x80x9cpaddlexe2x80x9d, xe2x80x9cislandxe2x80x9d, or xe2x80x9cdie mounting padxe2x80x9d upon which the die is mounted. In addition, inner leads are configured to approach the die edges having electrically conductive connection (bond) pads. The bond pads are input/output (I/O) electrodes of the die circuitry which enable connection through inner and outer leads to electronic apparatus. The inner leads and bond pads are normally connected by fine gold wires to provide power supply, ground and various signal connections. The die, connecting wires, and inner leads are then encapsulated to form a package which has outer leads which can be connected to an electrical apparatus such as a circuit board.
In a typical leads-over-chip (LOC) configuration, the die is mounted to the lead frame leads. Some or all of the lead frame leads overlie portions of the die and are connected to bond pads which may be centrally located or positioned near the periphery of the active die surface. A layer of insulative material such as adhesive tape is typically used to electrically insulate the overlying leads from the active die surface. Alternately, a multi-layer lead frame or a lead frame plus an additional mounting substrate may be used to provide the die support, as well as the inner leads to be mounted atop the die.
Regardless of the particular configuration of the wire-bonded device, the length-to-width ratio of the fine wires and inner leads is relatively high, and the wires and leads function as inductors to cause interference and cross-talk. Other factors which increase inductive interference include denser packing of leads and operation at higher clock speeds.
Various solutions for overcoming this deficiency in semiconductor construction have been proffered and typically include the addition of decoupling capacitors.
One approach has been to install separate decoupling capacitors on a circuit board and wire them across the power supply and return connections to the semiconductor device. In such designs, the relatively long distance between capacitors and the semiconductor die reduces the effectiveness of the capacitors, and may even increase the deleterious inductance. Exemplary decoupling capacitors for external connection to a packaged device are shown in U.S. Pat. No. 5,155,656 to Narashimhan et al., for example.
Various attempts have been made to more effectively decouple inductance by positioning the capacitor(s) more closely to the die. For example, an early method is shown in U.S. Pat. No. 3,460,010 to Domenico et al., in which the inactive side of the chip is subjected to multiple diffusion steps, and a capacitative layer is formed on and in the die. Other patents showing a capacitor within a die structure include U.S. Pat. Nos. 3,538,397 and 3,772,097 to Davis, U.S. Pat. No. 3,769,105 to Chen et al., U.S. Pat. No. 4,737,830 to Patel et al., U.S. Pat. No. 4,777,518 to Mihara et al. and Japanese Patent No. Application No. Sho 61[1986]-73367. The manufacturing processes shown in these references are expensive and complex, requiring a significant number of extra production steps. In addition, their effectiveness in actual use is somewhat less than desired.
Other methods for locating a capacitor close to the semiconductor die have been tried. For example, a separate capacitance structure has been attached to either of the xe2x80x9cactivexe2x80x9d die surface, the mounting surface of the die, a substrate, or to the lead frame. Exemplary of such designs are U.S. Pat. No. 4,410,905 to Grabbe, U.S. Pat. No. 5,281,556 to Shimizu et al., U.S. Pat. No. 4,656,605 to Clayton, U.S. Pat. No. 5,212,402 to Higgins III, U.S. Pat. No. 5,266,821 to Chern et al., U.S. Pat. No. 5,103,283 to Hite, and U.S. Pat. No. 4,994,936 to Hernandez.
In Japanese Patent No. Disclosure No. 4-188759 of Tachibana, a separate conductive member is interleaved with the lead frame paddle to form a capacitor. The separate member and paddle are respectively connected to the ground and Vcc bond pads of the overlying die. Somewhat similar structures using multi-layered capacitor construction are shown in German Pat. No. DE 3626151 A1 to Goetz, Japanese Patent No. Publication JP3165549A of Sato, Japanese Patent No. Publication No. JP4188759 of Masanori, Japanese Patent No. Publication No. JP4162657 of Hiroyuki, Japanese Publication No. JP3276747 of Natsuko, U.S. Pat. No. 5,140,496 of Heinks et al., U.S. Pat. No. 4,891,687 of Mallik et al., U.S. Pat. No. 4,965,654 of Kamer et al., U.S. Pat. No. 4,680,613 of Daniels et al., and Shinko catalogue, Hyperquad Series Types, Three Metal Layer QFP (1994).
In U.S. Pat. No. 5,444,600 to Dobkin et al. is shown a capacitor formed by interdigitated portions of a lead frame. Multiple semiconductor dies are mounted on separate paddles such that a ground connection to a first capacitor section and a power supply connection to a second capacitor section of the same capacitor couple are made from different semiconductor dies.
U.S. Pat. No. 5,105,257 of Michii describes a lead frame construction including a planar ground lead, a portion of which is attached to a die, and two power supply leads, one on each side of the semiconductor die.
The invention comprises an interdigitated lead frame paddle or bus configuration for integrated circuit (IC) devices such as dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, read only memory (ROM) chips, microprocessors and the like. The two separated portions of the conductive lead frame paddle are respectively connected to the power supply (Vss) and ground (Vcc) buses or bond pads to provide capacitative protection from inductive spikes in the ground and power supply circuits.
In a conventional semiconductor device assembly, the two-part lead frame paddle provides support for the die mounted thereon and acts as a source of decoupling capacitance for the power supply and ground circuits.
In a LOC-type configuration assembly, the separated lead frame portions comprise an interdigitated power supply bus and a ground bus which overlie the die and provide decoupling capacitance in the power supply and ground circuits.